1. Field of the Invention
The present invention relates to an information processing device and method, and particularly relates to an information processing device and method wherein hardware resources can be appropriately allocated to a software encoding unit and software decoding unit under an increased variety of conditions.
2. Description of the Related Art
Heretofore, there have been encoding units which subject image data to compression encoding (e.g. Japanese Unexamined Patent Application Publication No. 9-261633). Such encoding units can be realized with hardware, but can also be realized with a software program. In the case of a software encoding unit, for example, with a personal computer or the like, a software program is loaded into RAM (Random Access Memory), and the various processing included in the software program is executed with the CPU (Central Processing Unit). Also, encoded image data, encoded data generated by encoding, and various types of data generated during processing are held in the RAM as appropriate.
Similarly, there have been software decoding units which are decoding units that realize decoding of encoded data wherein image data is subjected to compression encoding using a software program. As with the software encoding units, with the software decoding units also, a software program is loaded into the RAM on a personal computer or the like, and various processing included in the software program is executed by the CPU. Also, the encoded data to be decoded, the image data to be decoded, and various types of data generated during processing are held in the RAM as appropriate.
In the case of a normal personal computer, between the CPU and RAM is connected by a shared bus. Generally, an operation frequency of a shared bus is low compared to an operation frequency of the CPU, and also the shared bus is used to transfer data between other devices. Accordingly, the RAM provided externally to the CPU has a large capacity, but the speed of reading or writing data is basically slower than the operation speed of the CPU. Also, depending on the congestion state of the shared bus, delays may become greater.
Conversely, a cache memory provided internally in the CPU is configured with a high-speed operating SRAM (Static Random Access Memory) or the like, and in a normal case, the operation frequency is higher than a shared bus, enabling reading or writing at a higher speed than with a RAM external to the CPU. Also, the cache memory is exclusively used by the CPU thereof, so the CPU can perform reading or writing at high speed without influence from the data transferring between other devices. However, from the point of cost, the cache memory capacity is limited to be small compared to a RAM provided external to the CPU. Also, in recent years, there have been computers wherein multiple CPUs operate in parallel.
In the case of software encoding units or software decoding units, allocating hardware resources such as CPU or memory is necessary, but it is necessary to allocate the hardware resources such as CPU or memory as to encoding processing and decoding processing appropriately so that the encoding processing or decoding processing efficiency is not reduced unnecessarily.